Si-MOS high-frequency semiconductor device and the manufacturing method of the same

ABSTRACT

An object of the present invention is to provide a sophisticated and highly reliable high-frequency Si-MOS semiconductor device having high ESD resistance. In the semiconductor device according to the present invention, lateral polysilicon diodes are formed and connected between high-frequency I/O signal line and the external supply voltage VDD, and between the ground GND and the high-frequency I/O signal line respectively. The forward direction of the diodes is the direction from the high-frequency I/O signal line to the VDD and the direction from the ground GND to the high-frequency I/O signal line respectively.

BACKGROUND OF THE INVENTION

[0001] The present invention relates to a high-frequency semiconductor device employing Si-MOS transistor, and especially relates to achievement of reliable and sophisticated high-frequency semiconductor device having high ESD (Electro Static Discharge) resistance.

SUMMARY OF THE INVENTION

[0002] Mobile phone and wireless LAN are widespread in application in recent years, so high-frequency semiconductor device, which is necessary in electric devices of these uses to improve their performance, size and costs, has been spotlighted. To achieve above high-frequency semiconductor device, III-V group compound semiconductor such as GaAs with high electron mobility is mainly used. However, with minimizing Si-MOS transistor rapidly in recent years, it becomes possible to form MOS (Metal-Oxide-Semiconductor) transistor of the gate length 0.2 μm or less, thereby transconductance Gm of MOS transistor is greatly improved so that high-frequency characteristics thereof is improved and becomes applicable to high-frequency device for GHz band. The invention achieves reliable and sophisticated high-frequency semiconductor device having high ESD (Electro Static Discharge) resistance with employing MOS transistor of Si.

[0003] A phenomenon in which electrostatically charged object contacts with other object(s) and causes electrical discharge is called ESD (Electro Static Discharge). The phenomenon happened at semiconductor device may destroy semiconductor elements. As theoretic models of ESD, discharge models of HBM (Human Body Model) presenting discharge from electrically charged human body to semiconductor elements, MM (Machine Model) presenting discharge from electrically charged machine to semiconductor element, and CDM (Charge Device Model) presenting discharge from charged semiconductor itself to grounded object are well-known. The current waveforms of HBM and CDM are shown in FIG. 1. In the figure, a current of approximately 1 A is caused for relatively long time (to 100 ns) in HBM and on the other hand, a large current of approximately 10 A is caused for a very short time (to 1 ns) in CDM.

[0004] As mentioned above, in case of ESD, impressing large current into the semiconductor element in a short time result in melt-down of the element due to heat caused by joule loss (this is referred as thermal destruction). Moreover, in case high voltage caused by ESD is applied to gate insulting layer of MOS transistor, which is typically and widely used in recent Si-LSI (Large-Scaled Integration) device, breakdown of the gate insulting layer may be caused. Accordingly, these kinds of device destruction caused by ESD, i.e. thermal destruction and breakdown of insulation, are problematic.

[0005] In order to prevent these destruction, various protection circuits are typically formed into the semiconductor device between internal circuit on a Si wafer and I/O pins so as not to transmit high voltage surge due to EDS to the internal circuit. Since the I/O pins are connected to I/O pads on the wafer through wire bonding, protection circuits are typically formed between the internal circuit and the I/O pads. Anyway, these protection circuits are commonly used and called as ESD protection circuits.

[0006] As ESD protection circuits, circuit wherein MOS transistors in OFF state are connected to I/O signal line is often used as referred in the article by M-D. Ker et.al., “IEDM, pp.889-892, 1996” (hereinafter article 1) for example. FIG. 2 is a circuit diagram illustrating typical ESD protection circuit. As shown in the figure, drain of N-type MOS transistor (hereinafter referred as NMOS) 31 wherein gate, source and P-well thereof are grounded and drain of P-type MOS transistor (hereinafter referred as PMOS) 32 wherein gate, source and N-well thereof are connected to external supply voltage (hereinafter referred as VDD) are connected to the I/O signal line connecting the I/O pad 30 and the internal circuit 100. Since MOS transistor 31 and 32 are both in OFF state, no current can flow through these transistors and give no effect on operation of the semiconductor device ordinarily. When a surge due to ESD is impressed from the I/O pad 30, parasitic bipolar transistor action shall be occurred in either of these transistors to form path for flowing, i.e. dispersing, large current from the drain to the source thereof.

[0007] With referring to FIG. 3, the parasitic bipolar transistor action of the MOS transistor will be described. It is assumed that surge 45 of positive voltage enters into the drain of NMOS 31 in here. First of all, a positive voltage of the surge is impressed to N+ diffusion layer 313 of drain. When the positive voltage of surge is increased, PN junction of N+ diffusion layer 313, which is reversely biased with this surge, causes breakdown and impact ionization occurs to generate a large amount of pair of electron and hole. Among generated pairs of electron and hole, the electron flow into the drain of positive voltage and the hole shall flow into grounded P-well 314. With presenting current owing to the flowing holes as I_(hole), and resistance of the P-well as R_(sub), the voltage difference of I_(hole)·R_(sub) shall appear in the depth direction within the P-well 314, thereby electric potential of P-well region 350 directly below a gate 311 of NMOS increases positively. At this time, in NPN parasitic bipolar transistor comprising the N+ diffusion layer 313 of drain, P-well region 350 directly below the gate and the N+ diffusion layer 312 of source, junction between the N+ diffusion layer 313 of drain and P-well region 350 is reversely biased and junction between the P-well region 350 and the N+ diffusion layer 312 of source is forwardly biased, thereby turning ON the NPN parasitic bipolar transistor. As described above, although the NMOS 31 is ordinarily in OFF state because the gate 311 is grounded, the positive is voltage of ESD surge 45 turns ON the NPN parasitic bipolar so that large current can be flown as shown with arrow 333. In addition, the positive voltage of surge is also applied to the drain of PMOS 32 and biases diode junction between the drain and N-well forwardly, thereby the diode junction is turned ON to disperse a current to the N-well.

[0008] Similarly, when ESD of negative voltage is impressed to the I/O pad 30, parasitic bipolar of PMOS 32 is turned ON to disperse a large current to the VDD. The negative voltage of surge is also applied to the drain of the NMOS 31 and turns ON a diode junction between the drain and P-well to disperse a current into the P-well.

[0009] Thus, with using the ESD protection circuit employing MOS transistor in OFF state can disperse a large current to the GND and the VDD so as to prevent thermal destruction and breakdown of the gate insulating layer with preventing that large current enters into internal circuit.

[0010] In order to accomplish the good ESD protection by the MOS transistors in OFF state, it is well known that layout of the MOS transistors should be noted. That is, in the MOS transistors for ESD protection, sufficient distance between gate electrode 60 and contact 63 connected to source or drain diffusion layer is required, i.e. certain distance 65 between gate and contact must be maintained as shown in FIG. 4. According to the article 1 by M-D. Ker et.al., the required distance 65 between gate and contact is 5 to 6 μm. With assuming the distance 65 between gate and contact to be “d”, the diameter of the contact 63 to be “c”, the width of source region 61 and drain region 62 situated between the gate electrodes 60 is obtained by an equation of “2d+c”. Since it is required to take the distance 65 between gate and contact enough in MOS transistor used as ESD protection element, the width of the source region 61 and the drain region 62 shall become larger. For example, in the design rule of 0.2 μm, typical diameter “c” of the contact 63 is approximately 0.2 μm, therefore, the width of the source region 61 and the drain region 62 obtained by “2d+c” is very large such as 10.2 to 12.2 μm. Moreover, in order to achieve sufficient ESD protection, the width, which appears in up and down direction in FIG. 4, of the gate of the MOS transistor should be at least 100 μm or more. In the design rule of 0.2 μm, parasitic capacitances of source/drain diffusion layer, i.e. depletion layer capacity of PN junction between source/drain diffusion layer and well, is commonly 1 fF/μm². Therefore, in the MOS transistor used as ESD protection element, parasitic capacitances of the source/drain diffusion layers for Si substrates, that is wells, is very large, such as 1.02 to 1.22 pF.

[0011] This large parasitic capacitances of ESD protection element had not been a problem in a semiconductor memory and a semiconductor logic device, however, it causes serious problem in the high-frequency semiconductor device using Si-MOSes. That is, since an impedance |z| due to capacitance C is presented by 1/(2πfC), the larger a frequency “f” becomes, i.e at high frequency, the smaller the impedance |z| becomes. When the capacity “C” further increases, impedance |z| of the capacity “C” is to be further reduced. That is, in a case where large capacitance of the drain diffusion layer is connected to high-frequency I/O signal line, the impedance due to this drain diffusion layer capacitance becomes very small.

[0012] As shown in the article of R. Groves “IEEE BCTM pp.149-152, 1999” (hereinafter article 2), high quality semiconductivie substrates having high resistivity such as substrates used for semiconductor device of GaAs compound are hardly available in Si semiconductor device. Accordingly, substrates of relatively low resistance are employed in Si semiconductor device. Therefore, in case of connecting ESD protection elements to the high-frequency I/O signal line as equivalent circuit in FIG. 5, the capacitance of drain diffusion layers in ESD protection element 33 and 34 are large so that the impedance at high frequency is very small. Moreover, due to that resistances 35 and 36 of Si substrate to which the capacitance 33 and 34 are connected are also small, most of high frequency signal Si on the high-frequency I/O signal line flow into the ESD protection element and are dispersed into the resistance of Si substrate.

[0013] As mentioned above, it has not been possible in the prior art to achieve a sophisticated and highly reliable high-frequency Si-MOS semiconductor device having high ESD resistance through forming ESD protection element.

[0014] The present invention provide a sophisticated and highly reliable high-frequency Si-MOS semiconductor device having high ESD resistance.

[0015] A high-frequency semiconductor device according to one embodiment of the present invention is characterized in that lateral polysilicon diodes are connected between high-frequency I/O signal line and external power supply VDD, and between ground GND and the high-frequency I/O signal line respectively, and forward direction of the lateral polysilicon diode is direction from the high-frequency I/O signal line to the external supply voltage VDD, and from the ground GND to the high-frequency I/O signal line respectively.

[0016] A high-frequency semiconductor device according to another embodiment of the present invention is characterized in that lateral polysilicon diodes to the number of “m” are connected between the high-frequency I/O signal line and externally supplied voltage VDD in series, and lateral polysilicon diodes to the number of “n” are connected between the ground GND and the high-frequency I/O signal line in series, and forward direction of lateral polysilicon diode is direction from the high-frequency I/O signal line to the external supply voltage VDD and from the GND to the high-frequency 1/O signal line, and with assuming the voltage of VDD as V_(dd),V_(dd)/(n+m) is preferably smaller than 1.1[V].

[0017] A high-frequency semiconductor device according to still other embodiment of the present invention is characterized in that at least a MOS transistor, a dielectric film of capacitor and a lateral polysilicon diode are provided on its substrate, and wherein the lateral polysilicon diodes are formed from the same polysilicon layer as a lower electrode of the capacitor, and wherein a gate electrode of MOS transistor is formed from another polysilicon layer. The gate electrode of the MOS transistor may be formed from the same polysilicon layer as the upper electrode of the capacitor.

[0018] A high-frequency semiconductor device according to still further embodiment of the present invention is characterized in that dielectric film of the capacitor or/and polysilicon layer used for upper electrode of the capacitor are left on and covering a PN junction of lateral polysilicon diodes, and edges of resist pattern used for injecting ion into the lateral polysilicon diodes are placed on the dielectric film or/and polysilicon layer on the PN junction.

[0019] A high-frequency semiconductor device according to further still other embodiment of the present invention is characterized in that a clamp circuit connected between the externally supplied voltage VDD and ground GND, wherein the clamp circuit operates to flow current within voltage lower than the absolute value of reverse-breakdown voltage of the lateral polysilicon diodes.

BRIEF DESCRIPTION OF THE DRAWINGS

[0020]FIG. 1 is a figure showing a current wave form of ESD (Electro Static Discharge);

[0021]FIG. 2 is the circuit diagram illustrating ESD protection circuit employing MOS transistor in OFF state;

[0022]FIG. 3 is a figure describing parasitic bipolar transistor action of MOS transistors;

[0023]FIG. 4 is a figure illustrating the distance between the gate and the contact of the MOS transistor;

[0024]FIG. 5 is an equivalent circuit diagram describing outflow of high-frequency signal through the capacitor of the drain diffusion layer of the MOS transistor;

[0025]FIG. 6 is a circuit diagram showing the ESD protection circuit according to the present invention;

[0026]FIG. 7(a) is a sectional view of the lateral polysilicon diode, and

[0027]FIG. 7(b) is a top view of it;

[0028]FIG. 8 is a figure showing voltage current characteristic of the lateral polysilicon diodes;

[0029]FIG. 9 is a figure showing the equivalent circuit describing outflow of the high-frequency signal through the parasitic capacitance for Si substrate and through the depletion layer capacity;

[0030]FIG. 10 is a figure showing ESD protection circuit according to the present embodiment;

[0031]FIG. 11 is a figure showing the influence of the presence of traps of deep energy in the tunnel effect between bands;

[0032]FIG. 12 is a figure showing the manufacturing process of the high-frequency semiconductor device according to the present invention;

[0033]FIG. 13 is a figure showing the manufacturing process following the FIG. 12;

[0034]FIG. 14 is a figure showing the manufacturing process following the FIG. 13;

[0035]FIG. 15 is a figure showing the manufacturing following the FIG. 14;

[0036]FIG. 16 is a figure showing the manufacturing process following the FIG. 15;

[0037]FIG. 17 is a figure showing the manufacturing process following the FIG. 16;

[0038]FIG. 18 is a figure showing other manufacturing process of the high-frequency semiconductor device according to the present invention;

[0039]FIG. 19 is a figure showing the manufacturing process following the FIG. 18;

[0040]FIG. 20 is a figure showing the manufacturing process following the FIG. 19;

[0041]FIG. 21 is a figure showing further still other manufacturing process of the high-frequency semiconductor device according to the present invention;

[0042]FIG. 22 is a figure showing the manufacturing process following the FIG. 21;

[0043]FIG. 23 is a figure showing the manufacturing process following the FIG. 22;

[0044]FIG. 24 is a figure showing the manufacturing process following the FIG. 23;

[0045]FIG. 25 is a figure showing further still other manufacturing process of the high-frequency semiconductor device according to the present invention;

[0046]FIG. 26 is a figure showing the manufacturing process following the FIG. 25;

[0047]FIG. 27 is a figure showing the manufacturing process following the FIG. 26;

[0048]FIG. 28 is a figure showing the manufacturing process following with the FIG. 27;

[0049]FIG. 29 is a figure showing an example of PN junction of lateral polysilicon diodes;

[0050]FIG. 30 is a figure showing other example of PN junction of lateral polysilicon diodes;

[0051]FIG. 31 is a figure showing still other example of PN junction of lateral polysilicon diodes;

[0052]FIG. 32 is a figure showing further still other example of PN junction of lateral polysilicon diodes;

[0053]FIG. 33 is a figure showing a protection circuit employing MOS transistor connected between VDD and GND;

[0054]FIG. 34 is a figure showing a clamp circuit connected between VDD and GND according to the present invention;

[0055]FIG. 35 is a figure showing an example of a clamp circuit connected between VDD and GND;

[0056]FIG. 36 is a figure showing other example of a clamp circuit connected between VDD and GND.

DETAILED DESCRIPTION Embodiment 1

[0057]FIG. 6 shows arrangement of ESD protection circuit for the high-frequency semiconductor device according to the present invention. FIG. 7 shows the structure of ESD protection element. In the ESD protection circuit according to the present embodiment, the lateral polysilicon diodes, which are formed with polysilicon (polycrystal silicon layer) for forming gate electrodes of the Si-MOS transistor, are employed. By the lateral polysilicon diodes, the clamp circuit for ESD is composed.

[0058] ESD protection through clamp circuit employing diodes is well known, hereinafter the function will be described. Diode 38 is connected between signal line, which connects an I/O pad 30 a and an internal circuit 100, and VDD (positive voltage supplied externally). The forward direction of the diode 38 is the direction from the signal line to the VDD as shown in FIG. 6(a). Further, another diode 37 is connected between GND and the signal line. The forward direction of the diode 37 is the direction from the GND to the signal line. When a positive voltage higher than VDD flows into the signal line in this diode clamp circuit, a diode 38 to which VDD is connected shall be turned ON and disperse the current toward the VDD. Until voltage of the signal line becomes lower than VDD, the diode 38 maintains its ON state. On the contrary, when a negative voltage lower than GND flows into the signal line, the diode 37 to which GND is connected shall be turned ON and disperse the current toward the GND. The diode 37 keeps ON state until a voltage of the signal line becomes higher than the GND. Thus, the clamp circuit can limit the voltage. Therefore, a positive high voltage ESD surge 45 a impressed to the signal line shall be dispersed to the VDD via the diode 38 (FIG. 6(b)). On the other hand, a negative high voltage ESD surge 45 b impressed to the signal line is dispersed to the GND via the diode 37 as shown in FIG. 6(c), thereby preventing the destruction of the internal circuit 100, to which the signal line is connected, from the ESD.

[0059] According to the article by A. Z. Wang et.al. “IEEE BCTM pp.46 to 49. 1999” (hereinafter article 3), the clamp circuit employing diodes also has serious disadvantages. In a case where the voltage of VDD is impressed to the signal line at normal operation wherein no ESD is occurred, the voltage of the signal line may be certain higher than VDD due to that supplied VDD varies (Normally, variation of ±10% is permitted in the industrial standard). In this case, the diode connected to VDD is turned ON, and a large leakage current flows through the diode. Therefore, it was difficult to use the clamp circuit employing diode for ESD protection.

[0060] Next, the description of lateral polysilicon diodes which is employed in the present invention is given. As shown in the FIG. 7, the lateral polysilicon diodes is made by forming PN junction laterally with forming P-type region 85 and N-type region 86 by injecting ion into a polysilicon film 84 which is formed on an insulating layer 82 of silicon oxide. As presented in the article by M. Dutoit et.al. “J. Electrichem. Soc. Vol.125, No.10, pp.1648 to 1651,1978” (hereinafter article 4), lateral polysilicon diodes has been studied since 1970's. Other than the article 4 by M. Dutoit et.al., many studies has been done. As an example of application to the semiconductor device, the article of Y. Miyawaki et.al. “IEEE J. Solid-State Circuits, vol.34, pp.1551 to 1556, November 1999” (hereinafter article 5) in which step-up circuit of flash memory which is a nonvolatile memory is enumerated. As shown in the study examples, lateral polysilicon diodes have an advantage that their parasitic capacitances is small because they are isolated from the Si substrates by the insulating layer of silicon oxide or the like. In the application to the step-up circuit of the flash memory shown in the article 5, a high efficiency step-up circuit is achieved with taking an advantage that there is no body effect with the lateral polysilicon diodes. Although the lateral polysilicon diodes have such advantages, they also have a serious problem as revealed in the many researches. That is, unlike to monocrystal silicon, polysilicon has a lot of defects and large grain size so that deep trap of energy level is formed and a reverse bias leakage current 72 is very large as shown in FIG. 8. In FIG. 8, forward bias leakage current 71 is also shown for reference. Though the monocrystal silicon shows ideal diode characteristics, since large current is leaked as shown in FIG. 8, the lateral polysilicon diodes could not be applied for a semiconductor logic device in which lower power consumption and lower leakage current are required. It was not also possible to apply to the semiconductor logic device because the leakage current causes mis-operation such as inversion between “1” and “0”. Further, a problem concerning with durability is critical. Polysilicon, which has a lot of defectives by nature of polycrystal, was not ensure reliability for enduring ON/OFF switching frequencies expected in life of ten years as typical semiconductor devices. Therefore, the lateral polysilicon diodes can not be applied to the logic device in view of reliability. In the article 5, lateral polysilicon diodes are applied not to a general circuit of the flash memory but to the step-up circuit. In the step-up circuit, large leakage current of lateral polysilicon diodes is not problematic. Moreover, the step-up circuit only operates during writing and deleting of the flash memory, so that frequencies of ON/OFF switching is several digits fewer than that of typical semiconductor device. Only for the step-up circuit supporting these conditions, the lateral polysilicon diodes can be applicable.

[0061] As described above, it was difficult to use a diode, especially a lateral polysilicon diode, as an element for the ESD protection circuit conventionally. The present invention is directed to solve these problems in the prior art through the following methods, and achieve a sophisticated and highly reliable semiconductor device having high ESD resistance in the high-frequency device employing with Si-MOS transistor for the first time.

[0062] In the present invention, a clamp circuit which employs lateral polysilicon diodes as ESD protection elements is attached only to high-frequency I/O signal line among all I/O signal lines of the high-frequency device employing with Si-MOS transistor. The prior art ESD protection circuit may be attached to other signal line with no high-frequency signals.

[0063] In the high-frequency I/O signal line, the DC bias voltage can be set to any preferable voltage. Therefore it is possible to apply certain voltage between VDD and GND instead of VDD as the DC bias voltage. By designing a bias circuit in such manner, a voltage of signal line shall not become higher than VDD even if VDD varies. As a result, a problem discussed in the article 3 in which diode is turned ON due to the variation of VDD in the clamp circuit employing diode can be solved. Therefore, the clamp circuit employing with diodes can be applied for the ESD protection.

[0064] Moreover, the high-frequency I/O signal line to which the lateral polysilicon diodes is connected supplies only bias voltage as DC circuit operation, therefore it shall not cause mis-operation even if a large reverse bias leakage current flows through the lateral polysilicon diodes. Therefore, the reverse bias leakage current in the lateral polysilicon diodes has not cause a problem so that the lateral polysilicon diodes can be used as protection element of clamp circuit. Though the bias voltage on the high-frequency circuit varies depend on the reverse bias leakage current, the bias voltage can be set with assuming this variation caused by the reverse bias leakage current. Thus, a large reverse bias leakage current of the polysilicon diode has no influence on the high-frequency characteristic of the signal line and the internal circuit at all, thereby preventing mis-operation to realize highly reliability. Again it should be noted, as mentioned above, lateral polysilicon diodes could not be used as a protection element for clamp circuit in the logic device that operates at DC voltage.

[0065] The ESD protection element operates only when ESD surge is impressed, so it requires much fewer reliability than that of the logic element which switches frequently. Therefore, it becomes possible to use lateral polysilicon diodes, which had not been ensured reliability for enduring ON/OFF switching operation to be expected in ten years since it includes a lot of defects due to the polycrystal, as ESD protection element.

[0066] The use of the lateral polysilicon diodes as ESD protection element decrease the parasitic capacitances between the diode and Si substrates, i.e. wells, dramatically, thereby preventing high-frequency signal leaking into the Si substrate of low resistance via the parasitic capacitances. As shown in FIG. 7, the cross wise length of the lateral polysilicon diodes is determined with the region to form PN junction and the region to form electrodes for P-type and N-type region 85 and 86 (that is, the required region to form a contacts 88 connected to P-type and N-type regions 85 and 86) and it is approximately 5 μm at most. With assuming width of the diode to be 100 μm as same as the above example of the MOS transistor, it could be thought that a conductor having its area S=500 μm² (S=5 μm×100 μm) is counterposed to Si substrate interposing the insulating layer of silicon oxide. With assuming the thickness “d” of the insulating layer to be 0.35 μm, the parasitic capacitances “C” between Si substrate and the conductor, i.e. the lateral polysilicon diodes, is obtained by the equation C=ε_(ox)·d/S (ε_(ox) is a dielectric constant of insulating layer (SiO₂)), so the capacitance C is 0.05 pF for one diode. The value is reduced to {fraction (1/20)}(0.5%), compared with 1.02 to 1.22 pF of the parasitic capacitances for MOS transistors in the prior art ESD protection circuit. It means that impedance due to the parasitic capacitances becomes 20 times or more than that of ESD protection element employing with MOS transistor at high-frequency, thereby preventing completely that high-frequency signals are passed through the parasitic capacitances and flow into the Si substrate. Thus, loss of the signal at the low resistance Si substrate shall be decreased dramatically. Accordingly it is achieved a sophisticated and highly reliable high-frequency semiconductor device having high ESD resistance, preventing destruction of Si-MOS transistor in the device without deteriorating high frequency characteristics.

[0067] As the parasitic capacitances along with lateral polysilicon diodes, there is depletion layer capacitance 39 and 40 of PN junction in addition to parasitic capacitances 41 and 42 between a Si substrate as shown in equivalent circuit diagram of FIG. 9. In a case where PN junction is made by the following methods, the impurity concentration often becomes very high such as approximately 10²⁰ cm⁻³, and depletion layer capacitance becomes relatively high. In a case where lateral polysilicon diodes is used for the prior art semiconductor device, the total parasitic capacitances, including the depletion layer capacitance, is important. However, as mentioned above, in the high frequency device employing with Si-MOS transistor, in which loss of the high-frequency signals at the low resistance Si substrate (diagrammatically shown as resistances 33 and 34 in FIG. 9) shall cause a problem, it is more important to reduce the parasitic capacitances between Si substrate.

[0068] Therefore, by employing with clamp circuit using lateral polysilicon diodes as ESD protection circuit, the present invention satisfies the request, raised with the high-frequency semiconductor device employing Si-MOS transistors, to reduce not total parasitic capacitances but the parasitic capacitances between the Si substrate. At the same time, as mentioned above, the present invention is also directed to and solves various problems preventing application of lateral polysilicon diodes in the prior art, and has new important effects and novelty.

[0069] As described above, the clamp circuit, which uses the lateral polysilicon diodes as an ESD protection element, is formed only on high-frequency I/O signal line among all I/O lines of the high-frequency device employing with Si-MOS transistor, thereby preventing destruction of Si-MOS transistor without causing mis-operation and deteriorating high frequency characteristics. Therefore a sophisticated and highly reliable high frequency semiconductor device with high ESD resistance is achieved.

Embodiment 2

[0070] In the present embodiment, as shown in FIG. 10, “m” pieces of lateral polysilicon diodes 38 a, 38 b, . . . , 38 m are connected in series between high-frequency I/O signal line which connects high-frequency signal I/O pad 30 a with the internal circuit 100 and VDD (positive voltage supplied externally). The forward direction of these diodes is the direction from the high-frequency I/O signal line to the VDD. Further, “n” pieces of lateral polysilicon diodes 37 a, 37 b, . . . , 37 n are connected in series between the ground (GND) and the high-frequency I/O signal line. The forward direction of these diodes is the direction from the GND to the high-frequency I/O signal line.

[0071] With representing the voltage of VDD as V_(dd), the total number (m+n) of lateral polysilicon diodes is desired to meet the following equation (1).

V _(dd)/(m+n)<1.1[V]  equation (1)

[0072] In the lateral polysilicon diode, PN junction is formed laterally. But practically, as described in later, a “i” region in which few or no impurities are doped is typically formed between “P” and “N” region to improve characteristic of diode. Because of this PIN junction, such a diode is called PIN diode and appears in the article of S. M. Sze, “Physics of Semiconductor Devices pp.117” (hereinafter article 6) for example. When a voltage is applied to the PIN type lateral polysilicon diodes, most of applied voltage is impressed to “i” region of high resistance. When it is assumed that a reverse voltage is impressed, and the impressed voltage to the “i” region becomes larger than band gap voltage of Si (approx. 1.1 [V]), energy band shall be shifted larger than the band gap of Si in the “i” region, thereby causing so called “tunnel effect” in which electrons in valence band passes through to conductive band (FIG. 11(b)). This is called “the tunnel effect between bands” as described in the publication entitled “Flash memory technological handbook” from science forum Inc. (hereinafter article 7). As mentioned above, polysilicon has a lot of defects and large grain size so that deep trap of energy level is formed. Thus, when the tunnel effect between bands are caused, leakage current at reverse bias shall be increased dramatically with encouraging generation of tunnel current via these deep trap of energy levels (refer to the FIG. 11(c)).

[0073] In the present embodiment, plurality of diodes are connected in series to configure a clamp circuit so that a reverse bias voltage impressed to each diode is less than band gap voltage of Si. Therefore tunnel effect between bands is prevented, thereby reducing DC current consumption with reducing reverse leakage current of the lateral polysilicon diodes. In the prior art, when plural number of diodes are connected in series, required voltage to turn ON the diodes is doubled, tripled, . . . , and results in increasing of power consumption. Further, diodes may not be turned ON since the required turn ON voltage becomes higher than the external supply voltage. According to the present invention, only reverse bias is impressed to the diode during ordinary operation of the device, and forward voltage is impressed when ESD is occurred. A surge voltage due to ESD is extremely higher than turn ON voltage of the diodes in series, therefore, the diodes is turned ON to flow current through them so as to protect the internal circuit from ESD. Thus, according to the present invention, it becomes possible to apply series connected diodes for the first time.

[0074] As described above, by applying the clamp circuit wherein lateral polysilicon diodes is employed as an ESD protection element only for the high-frequency I/O signal line among all I/O lines of the high-frequency device employing Si-MOS transistor circuit, it becomes possible to prevent destruction of Si-MOS transistor circuit element due to ESD without causing mis-operation and deteriorating high frequency characteristics. Therefore, a sophisticated and highly reliable high frequency semiconductor device with high ESD resistance is achieved.

[0075] The clamp circuit, wherein plurality of diodes are connected in series and therefore only applicable as ESD protection circuit, prevent a tunnel effect between bands when the lateral polysilicon diodes are reversely biased, thereby reducing reverse bias leakage current results in reduction of DC current consumption.

Embodiment 3

[0076] As for Embodiments 1 and 2, the clamp circuits of lateral polysilicon diode(s) are attached between the VDD and the signal line and between the GND and the signal line. However, the clamp circuit of lateral polysilicon diode(s) may be attached only to either of them, i.e. between the VDD and the signal line or between the GND and the signal line. The clamp circuit of lateral polysilicon diode(s) may be attached to either of them, and the prior art clamp circuit may be attached to another.

Embodiment 4

[0077] The manufacturing process of the high-frequency semiconductor device of embodiment 1, 2, and 3 are described with referring to FIGS. 12, 13, 14, 15, 16, and 17. FIGS. 12, 13, 14, 15, 16, and 17 shows manufacturing process of high-frequency semiconductor device in which NMOS transistor, PMOS transistor and lateral polysilicon diodes are formed on region 91 for NMOS, region 92 for PMOS and region 93 for diode respectively.

[0078] First of all, oxide film 2 for separation and insulation is formed on the Si substrate 1, and further, wells are formed at the region 91 and 92 by ion implantation (FIG. 12(a)).

[0079] Next, a gate insulating film 3 is formed, and further, a non-doped polysilicon layer 4 is formed (FIG. 12(b)).

[0080] Then a resist pattern 51 is formed, and impurity ion is injected into exposed region of the polysilicon layer 4 which is to be a gate electrodes of NMOS transistor as shown by arrow A. (FIG. 12(c)).

[0081] The resist pattern 51 is removed, and the polysilicon layer 4 is patterned to leave regions to be gate electrode of NMOS transistor, gate electrode of PMOS transistor and lateral polysilicon diodes with using another resist pattern (not shown) (FIG. 13(a)).

[0082] Resist pattern 52 is formed, and as shown by arrow B in the figure, ion implantation is carried out for forming LDD structure at source and drain of NMOS transistor (FIG. 13(b)).

[0083] The resist pattern 52 is removed and a resist pattern 53 is formed, and as shown by arrow C, ion implantation is carried out for forming LDD structure at source and drain of PMOS transistor (FIG. 13(c)).

[0084] The resist pattern 53 is removed and dielectric film sidewall 5 are formed on the lateral side of the polysilicon layer 4(FIG. 14(a)).

[0085] After that, resist pattern 54 is formed, and simultaneously with ion implantation into source and drain of NMOS transistor, ions are injected into a N-type region of the lateral polysilicon diodes as shown by arrow D (FIG. 14(b)).

[0086] Resist pattern 54 is removed and another resist pattern 55 is formed, and simultaneously with ion implantation into source and drain of PMOS transistor, ions are injected into a P-type region of the lateral polysilicon diodes as shown by arrow E (FIG. 14(c)).

[0087] Resist pattern 55 is removed and insulating film 6 for preventing SALICIDE (self-aligned silicide) is layered (FIG. 15(a)). Then, resist pattern 56 is formed (FIG. 15(b)), and the insulating film 6 is patterned (FIG. 15(c)) so that the dielectric film 6 on NMOS and PMOS is removed.

[0088] Accordingly, silicide wiring 7 is formed on gates, sources and drains of NMOS transistor and PMOS transistor by self-aligned silicide formation.

[0089] Hereinafter, interlayer insulating film 8 is layered (FIG. 16(b)), and contact hole 9 for NMOS transistor, PMOS transistor and the lateral polysilicon diodes are formed in the interlayer insulating film 8 (FIG. 17(a)).

[0090] A contact 10 of conductive material are formed within the contact hole 9, then metal wiring 11 is formed (FIG. 17(a)).

[0091] Hereinafter, processes for depositing interlayer insulating film, forming contact hole and contact (it is generally called “via hole” and “via” in second and succeeding layer) and forming metal wiring are repeated required time, thereby forming metal wiring having required number of layers. By forming passivation film for protection on the metal wiring of the uppermost layer, and then removing the protection film on the I/O pad, finally high frequency semiconductor device is completed.

[0092] In the above-mentioned description, ion implantation for source and drain of PMOS and ion implantation for the gate electrode of PMOS are performed simultaneously. However, the impurity ion implantation for the gate electrodes of PMOS transistor can be carried out immediately after or before injecting impurity ion into the gate electrodes of NMOS transistor (FIG. 12(c)).

Embodiment 5

[0093] Another example of the manufacturing process of the high-frequency semiconductor device of embodiments 1, 2, and 3 are described with referring to FIGS. 18, 19, and 20. FIGS. 18, 19, and 20 shows the manufacturing process of the high-frequency semiconductor device wherein NMOS transistor, PMOS transistor, and the lateral polysilicon diodes are formed on the region 91 for NMOS, region 92 for PMOS and region 93 for diode respectively.

[0094] First of all, the oxide film 2 for separation and insulation is formed on the Si substrate 1, and wells are formed at the region 91 and 92 by ion implantation (FIG. 18(a)).

[0095] Next, the gate insulating film 3 is formed, and further non-doped polysilicon layer 4 is formed (FIG. 18(b)).

[0096] Then the resist pattern 51 a is formed. Simultaneously with impurity ion implantation into exposed region of the polysilicon layer 4 which is to be a gate electrodes of NMOS transistor, ions are injected into a N-type region of the lateral polysilicon diodes as shown by arrow A (FIG. 18(c)).

[0097] The resist pattern 51 a is removed, and the polysilicon layer 4 is patterned to leave regions to be a gate electrode of NMOS transistor, a gate electrode of PMOS transistor and lateral polysilicon diode with using another resist pattern (not shown) (FIG. 19(a)).

[0098] Resist pattern 52 a is formed, and as shown by arrow B, ion implantation is carried out for forming LDD structure at source and drain of NMOS transistor (FIG. 19(b)).

[0099] The resist pattern 52 a is removed and another resist pattern 53 a is formed, and as shown by arrow C in the figure, ion implantation is carried out for forming LDD structure at source and drain of PMOS transistor (FIG. 19(c)).

[0100] The resist pattern 53 a is removed and dielectric film sidewall 5 are formed on the lateral side of the polysilicon layer 4 (FIG. 20(a)).

[0101] Resist pattern 54 a is formed, ions are injected into source and drain of NMOS transistor as shown by arrow D (FIG. 20(b)).

[0102] Further, the resist pattern 54 a is removed and another new resist pattern 55 a is formed. And simultaneously with ion implantation into source and drain of PMOS transistor, ions are injected into a P-type region of the lateral polysilicon diodes as shown by arrow E (FIG. 20(c)).

[0103] Hereinafter, silicide wiring, interlayer insulting film, a metal wiring and a passivation film are formed in the same manner as the embodiment 4.

[0104] In the above-mentioned description, ion implantation for source and drain of PMOS transistor and ion implantation for the gate electrodes of PMOS are performed simultaneously. However, the impurity ion implantation for the gate electrodes of PMOS transistor can be carried out immediately after or before injecting impurity ion into the gate electrodes of NMOS transistor (FIG. 18(c)).

Embodiment 6

[0105] Another manufacturing process of the high-frequency semiconductor device of embodiment 1, 2, and 3 are described with referring to FIGS. 21,22,23 and 24. FIGS. 21, 22, 23 and 24 show the manufacturing process of the high-frequency semiconductor device wherein NMOS transistor, PMOS transistor, a lateral polysilicon diodes and a capacitor are formed on the region 91 for NMOS, region 92 for PMOS, region 93 for diode and region 94 for capacitor respectively.

[0106] First of all, the oxide film 2 for separation and insulation is formed on the Si substrate 1, and wells are formed at the region 91 and 92 by ion implantation (FIG. 21(a)).

[0107] Further, polysilicon layer 14 in which N-type impurities are doped is formed (FIG. 21(b)).

[0108] This polysilicon layer 14 is patterned (FIG. 21(c)) to leave regions to be a lower electrode of the capacitor and a lateral polysilicon diodes.

[0109] Hereinafter, an dielectric film 15 for capacitor is laminated and patterned (FIG. 22(a)).

[0110] The gate insulating film 3 is formed, and further a non-doped polysilicon layer 24 is formed. Impurity ions are injected through a resist pattern into the polysilicon layer 24 to be a gate electrode of the NMOS transistor. Then the polysilicon layer 24 is patterned using the resist pattern so as to leave regions to be a gate electrode of NMOS transistor, a gate electrode of PMOS transistor and an upper electrode of capacitor (FIG. 22(b)).

[0111] A resist pattern 52 b is formed, and as shown by arrow B, ion implantation is carried out for forming LDD structure at source and drain of NMOS transistor (FIG. 22(c)).

[0112] The resist pattern 52 b is removed and another resist pattern 53 b is formed, and ion implantation is carried out for forming LDD structure at source and drain of PMOS transistor as shown by arrow C in the figure (FIG. 23(a)).

[0113] The resist pattern 53 b is removed and dielectric film sidewall 5 are formed on the lateral side of the polysilicon layer 14 and 24 (FIG. 23(b)).

[0114] Further, a resist pattern 54 b is formed. And, simultaneously with ion implantation into source and drain of NMOS transistor, ions are injected into a N-type region of the lateral polysilicon diodes as shown by arrow D (FIG. 24(a)).

[0115] Further, the resist pattern 54 b is removed and another new resist pattern 55 b is formed. And, simultaneously with ion implantation into source and drain of PMOS transistor, ions are injected into a P-type region of the lateral polysilicon diodes as shown by arrow E (FIG. 24(b)).

[0116] Hereinafter, silicide wiring, interlayer dielectric film, a metal wiring and passivation film are formed in the same manner as the embodiment 4.

[0117] In the above-mentioned description, ion implantation for source and drain of PMOS transistor and ion implantation for the gate electrode of PMOS transistor are performed simultaneously. However, the impurity ion implantation can be carried out for the gate electrodes of PMOS transistor immediately after or before injecting impurity ion into the gate electrodes of NMOS transistor (FIG. 22(b)).

Embodiment 7

[0118] Another manufacturing process of the high-frequency semiconductor device of embodiment 1, 2, and 3 are described with referring to FIGS. 25, 26, 27 and 28. FIGS. 25, 26, 27 and 28 show the manufacturing process of the high-frequency semiconductor device wherein NMOS transistor, PMOS transistor, a lateral polysilicon diodes and a insulating film of the capacitor are formed on the region 91 for NMOS, region 92 for PMOS, region 93 for diode and region 94 for capacitor respectively.

[0119] First of all, the oxide film 2 for separation and insulation is formed on the Si substrate 1, and wells are formed at the region 91 and 92 by ion implantation (FIG. 25(a)).

[0120] Further, polysilicon layer 14 in which N-type impurities are doped is formed (FIG. 25(b)).

[0121] Next, this polysilicon layer 14 is patterned to leave regions to be a lower electrode of dielectric film of the capacitor and a lateral polysilicon diodes (FIG. 25(c)).

[0122] Hereinafter, an dielectric film 15 for capacitor is laminated and patterned (FIG. 26(a)). At this time, the dielectric film 15 is left on the polysilicon layer 14 also at the place where the PN junction of the lateral polysilicon diode would be formed.

[0123] The gate insulating film 3 is formed, and further a non-doped polysilicon layer 24 is formed. Impurity ions are injected through a resist pattern into regions to be a gate electrode of the NMOS transistor. Then the polysilicon layer 24 is patterned using the resist pattern so as to leave regions to be a gate electrode of NMOS transistor, a gate electrode of PMOS and an upper electrode of the capacitor (FIG. 26(b)). At this time, the polysilicon layer 24 is left on the polysilicon layer 14 also at the place where the PN junction of the lateral polysilicon diode would be formed.

[0124] A resist pattern 52 c is formed, and ion implantation is carried out for forming LDD structure at source and drain of NMOS transistor as shown by arrow B (FIG. 26(c)).

[0125] The resist pattern 52 c is removed and another resist pattern 53 c is formed, and ion implantation is carried out for forming LDD structure at source and drain of PMOS transistor as shown by arrow C (FIG. 27(a)).

[0126] The resist pattern 53 c is removed, and dielectric film sidewall 5 are formed on the lateral sides of the polysilicon layers 14 and 24 (FIG. 27(b)).

[0127] After that, the resist pattern 54 c is formed, and simultaneously with ion implantation into source and drain of NMOS transistor, ions are injected into a N-type region of the lateral polysilicon diodes as shown by arrow D (FIG. 28(a)).

[0128] Further, the resist pattern 54 c is removed and another new resist pattern 55 b is formed, and simultaneously with ion implantation into source and drain of PMOS transistor, ions are injected into a P-type region of the lateral polysilicon diodes as shown by arrow E (FIG. 28(b)).

[0129] Hereinafter, silicide wiring, interlayer insulating film, a metal wiring and a passivation film can be formed in the same manner as the embodiment 4.

[0130] In the above-mentioned description, ion implantation for source and drain of PMOS transistor and ion implantation for the gate electrode of the PMOS transistor are performed simultaneously. However, the impurity ion implantation for the gate electrodes of PMOS transistor can be carried out immediately after or before injecting impurity ion into the gate electrodes of NMOS transistor (FIG. 26(b)).

Embodiment 8

[0131] The method of forming lateral polysilicon diodes in above-mentioned embodiment 4, 5, 6, and 7 will be further described in detail with referring to FIGS. 29, 30, 31, and 32.

[0132]FIG. 29(a) is a sectional view of the lateral polysilicon diodes, and FIG. 29(b) is a top view of it. Onto an insulating layer 82 of silicon oxide formed on Si substrate 81, a lateral polysilicon diode composed of P++ region 85 a heavily doped with P-type impurities and N++ region 86 a heavily doped with N-type impurities is formed. The lateral polysilicon diode is connected with metal wirings 89 via contacts 88.

[0133] Such a lateral polysilicon diodes are formed by injecting N-type impurity ions heavily into the region 86 a masking the region 85 a with a resist pattern (e.g., the resist pattern 54 in the embodiment 4), and further injecting P-type impurity ions heavily into the region 85 a masking the region 86 a with a resist pattern (e.g., the resist pattern 55 in the embodiment 4). Of course, the procedure of ion implantations of N-type and P-type may be changed.

[0134]FIG. 30(a) is a sectional view of the lateral polysilicon diodes, and FIG. 30(b) is a top view of it. Onto an insulating layer 82 of silicon oxide formed on Si substrate 81, a lateral polysilicon diode composed of P++ region 85 b heavily doped with P-type impurities, N+ region 87 b doped with N-type impurities and N++ region 86 b heavily doped with N-type impurities is formed. The lateral polysilicon diode is connected with metal wirings 89 via contacts 88.

[0135] The lateral polysilicon diode of FIG. 30 can be made as follows. Firstly, entire region of 85 b, 87 b and 86 b are formed from polysilicon doped with N-type impurities. Next, N-type impurity ions are heavily injected into the region 86 b masking the region 85 b and 87 b with a resist pattern, and further P-type impurity ions are heavily injected into the region 85 b masking the region 87 b and 86 b with a resist pattern. Of course, the procedure of ion implantations of N-type and P-type may be changed.

[0136] Moreover, according to the embodiment 7, it is possible to define precise boundaries between of the region 87 b and the region 86 b, and between the region 87 b and the region 85 b respectively, with using the polysilicon layer 24 and/or the dielectric film 15 formed on the polysilicon layer 14 at the place where the PN junction of the lateral polysilicon diode would be formed (FIG. 26(b)), without using resist pattern. It is possible to keep the width of the region 87 b constantly without varying the width due to declination of resist pattern, and reduce variation of diode characteristics. Therefore, it is possible to realize a high-frequency semiconductor device having high reliability.

[0137]FIG. 31(a) is a sectional view of the lateral polysilicon diodes, and FIG. 31(b) is a top view of it. Onto the insulating layer 82 of silicon oxide formed on the Si substrate 81, a lateral polysilicon diode composed of P++ region 85 c heavily doped with P-type impurities, a region 87 c substantially non-doped and N++ region 86 c heavily doped with N-type impurities is formed. The lateral polysilicon diode is connected with metal wirings 89 via contacts 88.

[0138] The lateral polysilicon diode of FIG. 31 can be made as follows. Firstly, entire region of 85 c, 87 c and 86 c are formed from non-doped polysilicon. Next, N-type impurity ions heavily injected into the region 86 c masking the region 85 c and 87 c with a resist pattern, and further P-type impurity ions are heavily injected into the region 85 c masking the region 87 c and 86 c with a resist pattern. Of course, the procedure of ion implantations of N-type and P-type may be changed.

[0139] Moreover, according to the embodiment 7, it is possible to define precise boundaries between of the region 87 c and the region 86 c, and between the region 87 c and the region 85 c respectively, with using the polysilicon layer 24 and/or the dielectric film 15 on the polysilicon layer 14 to be the lateral polysilicon diodes, without using resist pattern. It is possible to keep the width of the region 87 c constantly without varying the width due to declination of resist pattern, and reduce variation of diode characteristics. Therefore, it is possible to realize a high-frequency semiconductor device having high reliability.

[0140]FIG. 32(a) is a sectional view of the lateral polysilicon diodes, and FIG. 32(b) is a top view of it. Onto the insulating layer 82 of silicon oxide formed on the Si substrate 81, a lateral polysilicon diode composed of P++ region 85 d heavily doped with P-type impurities, a region 87 d heavily doped with P-type and N-type impurities and N++ region 86 d heavily doped with N-type impurities is formed. The lateral polysilicon diode is connected with the metal wirings 89 via the contacts 88.

[0141] The lateral polysilicon diode is formed by injecting N-type impurity ions heavily into the region 87 d and 86 d masking the region 85 d with a resist pattern, further by injecting P-type impurity ions heavily into the region 85 d and 87 d masking the region 86 d with a resist pattern. An impurity concentration of the region 87 d is determined by the differences of the concentration between injected N-type impurity ion and P-type impurity ion. Of course, the procedure of ion implantations of N-type and P-type may be changed.

Embodiment 9

[0142] As explained so far, in the present invention, the lateral polysilicon diodes 38 and 37 are formed and connected between the high-frequency I/O signal line and the external power supply VDD and/or between the high-frequency I/O signal line and the ground GND so as to prevent destruction of the internal circuit 100 due to ESD with dispersing positive high voltage ESD surge to the external power supply VDD, and negative high voltage ESD surge to the ground GND respectively.

[0143] Further, as shown in FIG. 33, it is assumed that the case where a protection circuit employing with MOS transistors is attached between the external power supply VDD and the ground GND in the high-frequency semiconductor device having ESD protection circuit employing lateral polysilicon diodes.

[0144] In FIG. 33, gate, source and P-well of NMOS transistor 46 are grounded to GND, and its drain is connected to the drain of PMOS transistor 47. On the other hand, gate, source and N-well of PMOS 47 are connected to the external power supply VDD.

[0145] A positive high voltage ESD surge impressed to the high-frequency signal I/O pad 30 a is dispersed to the VDD through the lateral polysilicon diode 38. The positive voltage surge entered into the VDD is impressed to the source of PMOS 47 being in OFF state, and PN junction of the source diffusion layer thereof causes breakdown, therefore “parasitic bipolar transistor action” is occurred and the current flows into the GND.

[0146] At this time, the potential of VDD and the high-frequency I/O signal line rises to the breakdown voltage of PN junction of the source diffusion layer in PMOS 47. Therefore, a reverse high voltage, which equals to the breakdown voltage of PN junction of silicon, is impressed to the lateral polysilicon diodes 37 attached between the high-frequency I/O signal line and GND. Similarly, in a case where a negative high voltage ESD surge is entered into the high-frequency signal I/O pad 30 a, the reverse voltage is impressed to the lateral polysilicon diodes 38.

[0147] The lateral polysilicon diode is made from polysilicon which includes a lot of defects and traps of deep energy, thereby characteristics thereof is easily deteriorated in case of breakdown due to reverse high voltage. Therefore, it is impossible to protect the circuit against the next ESD surge.

[0148] Therefore, in the present embodiment, as shown in FIG. 34, a clamp circuit 48, which starts operating at lower voltage than reverse breakdown voltage of the lateral polysilicon diode, is attached between the external power supply VDD and the ground GND.

[0149] The positive high voltage ESD surge 45 a entered into the VDD shall be dispersed to the GND through the clamp circuit 48 which is turned ON by a slight increase of the potential of the VDD (FIG. 34(b)). Since a turn ON voltage of the clamp circuit 48 is smaller than reverse breakdown voltage of the lateral polysilicon diodes 37, a voltage of VDD shall not become higher. Therefore, a voltage of the high-frequency I/O signal line is kept below the absolute value of the reverse breakdown voltage of the lateral polysilicon diode 37, thereby preventing reverse breakdown of the diode 37 and deterioration of the diode 37 due to the reverse breakdown.

[0150] In case of dispersing negative high voltage surge 45 b entered into the high-frequency signal I/O pad 30 a to the GND through the lateral polysilicon diodes 37, it is also possible to prevent deterioration of the lateral polysilicon diode 38 with preventing reverse breakdown of the diode 38 similarly (FIG. 34(c)).

[0151] As described above, according to the present embodiment, it is possible to protect the internal circuit against multiple impressions of ESD surge with preventing deterioration of the lateral polysilicon diode with preventing reverse breakdown thereof.

[0152] The embodiment of the clamp circuit 48 will be described with referring to FIG. 35 and 36.

[0153] In FIG. 35, the clamp circuit 48 comprises ESD detection circuit 75, inverter 76 and NMOS transistor 77. An output of the ESD detection circuit 75 is connected to the inverter 76, and the output of the inverter 76 is connected to the gate of NMOS 77. NMOS 77 has wide gate so as to allow a large current.

[0154] The detection circuit 75 immediately detects sudden increase of VDD voltage due to the impression of ESD surge, and NMOS 77 is turned ON via the inverter 76. Therefore it is possible to disperse a large current from VDD to GND through the NMOS 77.

[0155] Accordingly, the voltage of VDD as well as high-frequency I/O signal line shall not increase, thereby preventing that a high voltage larger than reverse breakdown voltage shall be impressed to the lateral polysilicon diodes 37 which is attached between the high-frequency I/O signal line and GND.

[0156] In FIG. 36, the clamp circuit 48 comprises “x” pieces of diode 78 attached in series, and forward direction of the diodes is the direction from the VDD to the GND, thereby enables to flow the large current from VDD to GND when the potential difference between VDD and GND becomes “x” times of the turn ON voltage of the diode 78.

[0157] By choosing “x” so that “x” times of the turn ON voltage of the diode 78 should be smaller than the reverse breakdown voltage of the lateral polysilicon diode, the voltage of VDD and the high-frequency I/O signal line can be kept lower than the reverse breakdown voltage of the lateral polysilicon diodes, so that the characteristic of the lateral polysilicon diodes shall not be deteriorated.

[0158] In addition to the lateral polysilicon diodes, made of typical PN junction diodes can also be used as the diode 78 and.

[0159] According to the present invention, a clamp circuit employing lateral polysilicon diodes as ESD protection element is attached to the high-frequency I/O signal line among all I/O lines of high-frequency device employing Si-MOS transistor so as to decrease the parasitic capacitances between the diode and Si substrate, thereby preventing high-frequency signal leaking into the Si substrate via the parasitic capacitances. Therefore it is possible to achieve sophisticated and highly reliable high frequency semiconductor device.

[0160] A DC bias voltage of high-frequency I/O signal line can be set between VDD and GND, thereby keeping the voltage of the signal line lower than that of VDD to prevent the diode being turned ON even if VDD varies. Therefore a sophisticated and highly reliable high frequency semiconductor device with high ESD resistance can be achieved.

[0161] Further, the clamp circuit employing lateral polysilicon diodes as ESD protection element is attached to the high-frequency I/O signal line among all I/O lines of high-frequency semiconductor device employing Si-MOS transistor. The high-frequency I/O signal line shall not cause mis-operation even if a large reverse bias leakage current flows through the lateral polysilicon diodes, since the signal line only supplies bias voltage at DC circuit operation. Therefore, the problem in caused by the large reverse bias leakage current of the lateral polysilicon diodes is solved, and a sophisticated and highly reliable high frequency semiconductor device with high ESD resistance is achieved employing the lateral polysilicon diodes as ESD protection element in the clamp circuit.

[0162] Moreover, the lateral polysilicon diodes of the clamp circuit operate only when ESD surge is impressed. Therefore, it is possible to use lateral polysilicon diodes, which had not been ensured reliability for ON/OFF switching operation to be expected in ten years in logic devices as the ESD protection elements.

[0163] Plurality of diodes are connected in series to configure the clamp circuit, thereby keeping a reverse bias voltage to be impressed to each diodes less than band gap voltage of Si (approx. 1.1 [V]). Therefore tunnel effect between bands is prevented, and thereby reducing DC current consumption with reducing reverse leakage current of the lateral polysilicon diodes.

[0164] A high-frequency semiconductor device employing with lateral polysilicon diodes as ESD protection element wherein lateral polysilicon diodes are formed from polysilicon layer for forming lower electrodes of the capacitor, and gate electrodes of MOS transistor are formed from another polysilicon layer. Therefore, it becomes possible to optimize forming condition such as thickness and impurities concentration and the like of polysilicon layers suitable for the MOS transistor and the lateral polysilicon diodes respectively and high reliability thereof can be realized simultaneously.

[0165] By leaving the dielectric film to form the capacitor and/or polysilicon layer to form the upper electrode of the capacitor on PN junction of the lateral polysilicon diodes, it becomes possible to reduce variation of diode characteristics due to declination of resist pattern, and realize a high-frequency semiconductor device having high reliability.

[0166] In addition, the “i” region can be formed at the PN junction of the lateral polysilicon diode by leaving the dielectric film to form the capacitor and/or polysilicon layer to form the upper electrode of the capacitor on PN junction of the lateral polysilicon diodes and blocking ion implantation with the film and/or the layer. Moreover, it becomes possible to keep the width of the “i” region of the PIN junction constantly without varying the width due to declination of resist pattern so that the diodes having good and uniform qualities are obtained.

[0167] Further, the clamp circuit, which starts operating at lower voltage than reverse breakdown voltage of the lateral polysilicon diodes, is attached between the external power supply VDD and the ground GND. Therefore reverse voltage breakdown of the lateral polysilicon diodes are prevented to avoid deterioration of their characteristics so that it becomes possible to protect the interval circuit against multiple impression of ESD surge.

[0168] While there has been described what is at present considered to be preferred embodiment of the invention, it will be understood that various modifications may be made therein, and it is intended to cover in the appended claims all such modifications as fall within the true spirit and scope of the invention. 

What is claimed is:
 1. A high-frequency semiconductor device comprising a Si MOS transistor and a lateral polysilicon diode both formed on a substrate, wherein the lateral polysilicon diode connects a high-frequency I/O signal line and externally supplied voltage VDD, and forward direction of the lateral polysilicon diode is direction from the high-frequency I/O signal line to the externally supplied voltage VDD.
 2. A high-frequency semiconductor device of claim 1, further comprising a lateral polysilicon diode on the substrate, wherein the lateral polysilicon diode connects ground GND and a high-frequency I/O signal line, and forward direction of the lateral polysilicon diode is direction from ground GND to the high-frequency I/O signal line.
 3. A high-frequency semiconductor device of claim 2, wherein lateral polysilicon diodes to the number of “m” are connected between the high-frequency I/O signal line and externally supplied voltage VDD in series, lateral polysilicon diodes to the number of “n” are connected between ground GND and the high-frequency I/O signal line in series, and with assuming the voltage of VDD as V_(dd), V_(dd)/(n+m) is smaller than 1.1 (V).
 4. A high-frequency semiconductor device of claim 1, wherein a lateral polysilicon diode is not connected to a signal line other than a high frequency I/O signal line.
 5. A high-frequency semiconductor device of claim 1 further comprising a capacitor having a lower electrode and an upper electrode both formed with polysilicon, wherein the lateral polysilicon diode and the lower electrode of the capacitor are formed from same polysilicon layer, and gate electrode of the MOS transistor is formed from another polysilicon layer.
 6. A high-frequency semiconductor device of claim 1 further comprising a capacitor having a lower electrode and an upper electrode both formed with polysilicon, wherein the lateral polysilicon diode and the lower electrode of the capacitor are formed from same polysilicon layer, and gate electrode of the MOS transistor and the upper electrode of the capacitor are formed from another polysilicon layer.
 7. A high-frequency semiconductor device of claim 5, wherein polysilicon layer to form the upper electrode of the capacitor is also left on and covering PN junction of the lateral polysilicon diode.
 8. A high-frequency semiconductor device of claim 5, wherein a dielectric layer to form the capacitor is also left on and covering PN junction of the lateral polysilicon diode.
 9. A manufacturing method of high-frequency semiconductor device having a MOS transistor, lateral polysilicon diodes and a capacitor on a substrate, and the lateral polysilicon diode connects a high-frequency I/O signal line and externally supplied voltage VDD, and the other lateral polysilicon diode connects ground GND and the high-frequency I/O signal line; wherein the lower electrode of the capacitor and the lateral polysilicon diode are formed from a first polysilicon layer, the insulating film of the capacitor is formed from a first dielectric layer, the upper electrode of the capacitor is formed from a second polysilicon layer, the first dielectric layer is also left on a certain region of the first polysilicon layer at which PN junction of the lateral polysilicon diode is to be formed, and an edge of a resist mask used for injecting ion into N-type region of the lateral polysilicon diode and an edge of a resist mask used for injecting ion into the P-type region of the lateral polysilicon diode are placed on the first dielectric layer being left.
 10. A manufacturing method of high-frequency semiconductor device having a MOS transistor, lateral polysilicon diodes and a capacitor on a substrate, and the lateral polysilicon diode connects a high-frequency I/O signal line and externally supplied voltage VDD, and the other lateral polysilicon diode connects ground GND and the high-frequency I/O signal line, wherein the lower electrode of the capacitor and the lateral polysilicon diode are formed from a first polysilicon layer, the insulating film of the capacitor is formed from a first dielectric layer, the upper electrode of the capacitor is formed from a second polysilicon layer, the second polysilicon layer is also left on a certain region of the first polysilicon layer at which PN junction of the lateral polysilicon diode is to be formed, and an edge of a resist mask used for injecting ion into N-type region of the lateral polysilicon diode and an edge of a resist mask used for injecting ion into the P-type region of the lateral polysilicon diode are placed on the second polysilicon layer being left.
 11. A manufacturing method of claim 9, wherein gate electrode of the MOS transistor is formed from the second polysilicon layer.
 12. A high-frequency semiconductor device of claim 1 further comprising a clamp circuit connected between the externally supplied voltage VDD and ground GND, wherein the clamp circuit operates to flow current within voltage lower than the absolute value of reverse bias breakdown voltage of the lateral polysilicon diode. 